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[Caml-list] Does Caml have slow arithmetics ?
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Date: -- (:)
From: Brian Hurt <bhurt@s...>
Subject: Re: [Caml-list] tail recursion and register poor Intel architecture
On Thu, 8 Jul 2004, Brandon J. Van Every wrote:

> Or implement more of what Intel's crufty architecture actually offers.
> For instance, supporting SSE would provide 8 additional 32-bit FPU
> registers.  

If you're using the MMX/SSE[123] registers, you can not be using the x87 
registers.  In addition, to move values between these registers (or the 
x87 registers) and the normal integer registers, you have to go via 
memory- i.e. write the value out to memory and read them back in again 
into the other register.  At which point you might as well be throwing 
them on the stack.

The large print giveth, and the small print taketh away.

> One doesn't have to use use the XMM registers for vectors,
> they could be used as scalars, and that's the more straightforward
> benefit of SSE architecture.  SSE2 allows for 64-bit FPU registers and
> also integer registers, of size 32-bit and 64-bit IIRC (but I haven't
> much cared about integer code).  

SSE2 is also only available on the P4s and the Opterons/Athlon-64s (AMD is 
the current crown holder for cool code names and dorky release names, 
having taken it away from HP.  Hammers and Snakes- cool code names.  
Sempron?  Give me a break).  Those of us with older computers would like 
to keep backward compatibility.

> For the record, I hate Intel's architectures.  They were talking about
> Merced when I was writing real code on DEC Alpha.  Alpha is dead for
> marketing reasons, not technical ones.  Meanwhile, Itanium is still
> handwaving.

Yes, but now it's the desperate handwaving of people trying to flag down a 
rescue helicopter.

> AMD also offers more registers on their newest chips.  I'm too fazed to
> remember the details right now; I do recall twice as many FPU registers.

The new iAMD-64 architecture in 64-bit mode has 16 general purpose 
registers (of which 14 are usable as such- the stack pointer and base 
pointer are both counted as general purpose registers), and 16 fp
registers (usable as both x87 and MMX/SSE[123] registers).

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