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ISQED06 Call for Papers - Deadline Extension - Oct 17
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Date: 2005-10-10 (18:03)
From: Jozwiak, L. <L.Jozwiak@t...>
Subject: ISQED06 Call for Papers - Deadline Extension - Oct 17
Due to an overwhelming number of requests from authors paper submission
deadline for ISQED'06 has been extended to Oct. 17th, 2005



7th International Symposium on


March 27-29, 2006.  San Jose, CA, USA

Extended Paper Submission Deadline:  October 17, 2005
Acceptance Notifications:  November 22, 2005
Final Camera-Ready paper:  January 3, 2006

ISQED is the pioneer and leading international conference dealing with
the design for manufacturability and quality issues front-to-back. 
ISQED spans three days, Monday through Wednesday, in three parallel
tracks, hosting near 100 technical presentations, six keynote speakers,
two-three panel discussions, workshops /tutorials and other informal
meetings. Conference proceedings are published by IEEE Computer Society
and hosted in the digital library. Proceedings CD ROMs are published by
ACM.  In addition, continuing the tradition of reaching a wider
readership in the IC design community, ISQED will continue to publish
special issues in leading journals. The authors of high quality papers
will be invited to submit an extended version of their papers for the
special journal issues.

Papers are requested in the following areas:

A pioneer and leading multidisciplinary conference, ISQED accepts and
promotes papers related to the manufacturing, VLSI design and EDA.
Authors are invited to submit papers in the various disciplines of high
level design, circuit design, test & verification, design automation
tools; processes; flows, device modeling, semiconductor technology, and
advance packaging.

1. Manufacturing, process, devices
	1.1 Design for Manufacturability & Quality (DFMQ)
	1.2 Effects of Technology on IC Design, Performance, Reliability, and
Yield  (TRD)

2. Design
	2.1 System-level Design, Methodologies & Tools (SDM)
	2.2 Package - Design Interactions & Co-Design  (PDI)
	2.3 Robust Device, Interconnect, and Circuits (RDIC)

	3.1 EDA Methodologies, Tools, & IP Cores; Interoperability  and
	3.2 Design Verification and Design for Testability (DVFT)
	3.3 Physical Design, Methodologies & Tools (PDM)

The details of various topics of paper submission is as follows:

Design for Manufacturability & Quality (DFMQ)

Analysis, modeling, and abstraction of manufacturing process parameters
and effects for highly predictable silicon performance.  Design and
synthesis of high complexity ICs:  signal integrity,  transmission line
effects, OPC, phase shifting,  and sub-wavelength lithography,
manufacturing yield and technology capability.  Design for
diagnosability,  defect detection and tolerance;  self-diagnosis,
calibration and repair.  Design and manufacturabilty issues for Digital,
analog, mixed signal, RF, MEMS, opto-electronic, biochemical-electronic,
and nanotechnology based ICs. Redundency and other yield improving
techniques. Design quality definitions and standards; design quality
metrics to track and assess the quality of electronic circuit design, as
well as the quality of the design process itself; design quality
assurance techniques.  Global, social, and economic implications of
design quality.  Design metrics, methodologies and flows for custom,
semi-custom, ASIC, FPGA, RF, memo
 ry, networking circuit, etc. with emphasis on quality.  Design metrics
and quality standards for SoC, and SiP.

Package - Design Interactions & Co-Design  (PDI)

Silicon and package co-design and impact on product quality. 3D design
challenges.  Electrical and thermal model of package and package-die
interactions.  SoC versus system in a package (SiP) tradeoffs.  di/dt
modeling techniques. MCM and other packaging techniques. Die and package
power delivery modeling and simulation, heat sink technology modeling,
design and optimization.

Design Verification and Design for Testability (DVFT)

Hardware and Software, formal and simulation based design verification
techniques to ensure the functional correctness of hardware early in the
design cycle. DFT and BIST for digital and SoC.  DFT for
analog/mixed-signal ICs and systems-on-chip, DFT/BIST for memories. 
Test synthesis and synthesis for testability.  DFT economics, DFT case
studies.  DFT and ATE.  Fault diagnosis,  IDDQ test,  novel test
methods,  effectiveness of test methods,  fault models and ATPG, and
DPPM prediction. SoC/IP testing strategies.

Robust Device, Interconnect, and Circuits (RDIC)

Device, substrate, interconnect, circuit , and IP block modeling and
simulation techniques;  quality metrics, model order reduction; CMOS,
Bipolar, and SiGe HBTs device modeling in the context of advanced
digital, RF and high-speed circuits.  Modeling and simulation of novel
device and interconnect concepts. Signal integrity analysis: coupling,
inductive and charge sharing noise; noise avoidance techniques. Power
grid design, analysis and optimization; timing analysis and
optimization; thermal analysis and design techniques for thermal
management.  Modeling statistical process variations to improve design
margin and robustness, use of statistical circuit simulators.
Power-conscious design methodologies and tools; low power devices,
circuits and systems; power-aware computing and communication; 
system-level power optimization and management. Design techniques for
leakage current management.

EDA Methodologies, Tools, & IP Cores; Interoperability  and Reuse(EDA)

EDA tools addressing design quality. Management of design process,
design flows and design databases. EDA tools interoperability issues and
implications. Effect of emerging technologies, processes & devices on
design flows, tools, and tool interoperability. Emerging EDA standards.
EDA design methodologies and tools that address issues which impact the
quality of the realization of designs into physical integrated circuits.
IP modeling and abstraction. Design and maintenance of technology
independent hard and soft IP blocks. Methods and tools for analysis,
comparison and qualification of libraries and hard IP blocks. Challenges
and solutions of the integration, testing, and qualifying of IP blocks
from multiple vendors. Third party testing of IP blocks. Risk management
of IP reuse. IP authoring tools and methodologies.

Physical Design, Methodologies & Tools (PDM)

Physical synthesis flows for correct-by-construction quality silicon,
implementation of large SoC designs.  Tool frameworks and datamodels for
tightly integrated incremental synthesis, placement, routing, timing
analysis and verification.  Placement, optimization, and routing
techniques for noise sensitivity reduction and fixing.  Algorithms and
flows for harnessing crosstalk-delay during physical synthesis.  Tool
flows and techniques for antenna rule and electromigration rule
avoidance and fixing.  Spare-cell strategies for ECO, decoupling
capacitance and antenna rule fixing.  Planning tools for predictable
high-current, low-voltage power distribution. Reliable clock tree
generation and clock distribution methodologies for Gigahertz designs. 
EDA tools, design techniques, and methodologies, dealing with issues
such as: timing closure, R, L, C extraction, ground/Vdd bounce, signal
noise/cross-talk /substrate noise, voltage drop, power rail integrity,
electromigration, hot car
 riers, EOS/ESD, plasma induced damage and other yield limiting effects,
high frequency effects, thermal effects, power estimation, EMI/EMC,
proximity correction & phase shift methods, verification (layout,
circuit, function, etc.).

Effects of Technology on IC Design, Performance, Reliability, and Yield 

Effect of emerging processes & devices on design's time to market,
yield, reliability, and quality.  Emerging issues in DSM CMOS: e.g.
sub-threshold leakage, gate leakage, technology road mapping and
technology extrapolation techniques.  New and novel technologies such as
SOI, Double-Gate(DG)-MOSFET, Gate-All-Around (GAA)-MOSFET,
Vertical-MOSFET, strained CMOS, high-bandwidth metallization, etc. 
Challenges of mixed-signal design in digital CMOS or BiCMOS technology,
including issues of substrate coupling, cross-talk and power supply
noise.  Significance of reliability effects such as gate oxide
integrity,  electromigration, ESD, etc.,  in relation to electronic
design.  Impacts of process technologies on circuit design and
capabilities (e.g. low-Vt transistors versus increased off-state
leakages) and the accuracy, use and implementation of SPICE models that
faithfully reflect process technologies. Successful applications of TCAD
to circuit design.

System-level Design, Methodologies & Tools (SDM)

Global, Social, and Economical Implications of Electronic System and
Design Quality. Emerging standards and regulations influencing system
quality. Emerging system-level design paradigms, methods and tools
aiming at quality. System-level design process and flow management.
System-level design modeling, analysis and synthesis, estimation and
verification for correct high-quality hardware/software systems.
Responsive, secure, and defect tolerant systems. New concepts, methods
and tools addressing system-level design complexity and multitude of
aspects. Methods and tools addressing the usage of technology
information and manufacturing feedback in the system-, RTL- and logic
level design. The influence of the nanometer technologies'
(application-dependent) yield and other issues on the system-, RTL- and
logic-level design. System-level trade-off analysis and multi-objective
(yield, power, delay, area ...) optimization. Effective and efficient
design, implementation, analysis and va
 lidation of large SoCs integrating IP blocks from multiple vendors.

Submission of Papers
Paper submission must be done on-line via the conference web site at Authors should submit FULL-LENGTH, original, unpublished
papers (Minimum 4, maximum 6 pages) along with an abstract of about 200
words.  Please check the as-printed appearance of your paper before
uploading. To permit a blind review,  do not include name(s) or
affiliation(s) of the author(s) on the manuscript and abstract.  The
complete contact author information  needs to be entered separately.
When ready to submit your paper have the following information ready:

I	Title of the paper
II	Name, affiliation, complete mailing address and phone, fax, and email
of the first author
III	Name, affiliations, city, state, country of additional authors
IV	Person to whom correspondence should be sent, if other than the 1st
V	Suggested area (as listed above)

The guidelines for the final paper format are provided on the conference
web site at Authors of the submitted papers must register
and attend the conference for their paper to be published.

Please note the following important dates:

Paper Submission Deadline:  October 17, 2005
Acceptance Notifications:  November 22, 2005
Final Camera-Ready paper:  January 3, 2006

The International Symposium on Quality Electronic Design (ISQED), is a
premier Design & Design Automation conference, aimed at bridging the gap
between and integration of, electronic design tools and processes,
integrated circuit technologies, processes & manufacturing, to achieve
design quality. ISQED is the pioneer and leading conference dealing with
design for manufacturability and quality issues front-to-back. The
conference provides a forum to present and exchange ideas and to promote
the research, development, and application of design techniques &
methods, design processes, and EDA design methodologies and tools that
address issues which impact the quality of the realization of designs
into physical integrated circuits. The conference attendees are
primarily designers of the VLSI circuits & systems (IP & SoC), those
involved in the research, development, and application of EDA/CAD Tools
& design flows, process/device technologists, and semiconductor
manufacturing speci
 alists including equipment vendors. ISQED emphasizes a holistic
approach toward design quality and intends to highlight and accelerate
cooperation among the IC Design, EDA, Semiconductor Process Technology
and Manufacturing communities.

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