HDCaml is a hardware description language embedded in OCaml.  Given a 
digital design in HDCaml, the tools will output a synthesizable Verilog 
netlist with PSL assertions for verification.

Though HDCaml is still in early beta, 0.2 has undergone a major cleanup 
of the API.  All comments are welcome.  To download...

   http://www.confluent.org/


To generate the [undocumented] example...

 > ocaml hdcaml.cma
         Objective Caml version 3.09.0
 

# Hdcaml.Example.all_prims ();;


Enjoy!

-Tom