]> IEEE International High Level DesignValidation and Test Workshop 2009 *November 4-6, 2009* *Grand Hyatt, San Francisco (Union Square)* Register at http://www.hldvt.com/09/registration.html before *October 7**th* to receive discounted registration rates. Book your hotel room in the heart of San Francisco at a discounted rate of $140. For the past 13 years, IEEE International High Level Design Validation and Test Workshop has been a platform for addressing emerging challenges in verification and test methodologies for ICs and systems. The workshop is an informal forum where EDA tool developers, academics, and industrial practitioners get together to discuss contemporary issues in verification, debug, synthesis, and test. *This year's program will feature….* · Keynote Address by *Sunil R. Shenoy* - Vice President, Intel Architecture Group, and General Manager, Microprocessor and Graphics Development - Intel Corporation · Seventeen Regular Papers · Panel: *SystemC Why: To Design or to Verify? What experts say?* · Special Session: *Innovative Industrial Practices* · Three Invited Sessions: · *RTL Validation and Debug*** · *High-Level Modeling and Validation*** · *Post-Silicon Validation and Debug* *Helpful Links:* Advance Program: http://www.hldvt.com/09/HLDVTAP09.pdf Hotel Information: http://www.hldvt.com/09/local.html Home Page: http://www.hldvt.com/09/index.html